Several previous projects at ZISS (e.g. e-Wifi) made it possible to push the limits of high accurate time synchronization down to the nanosecond range. Nevertheless, for packet oriented, cable based communication infrastructures, such as 100Base-TX Ethernet, a remaining issue was the inherently present delay asymmetry of the transmission lines.
The goal of the AEtas project was to create an out-of-band communication system that allows to measure and eventually mitigate this delay asymmetry.
The main source for delay asymmetry is the different propagation delay on transmit and receive path which cannot be measured by using conventional 100Base-TX Ethernet. The reason for this is that the unidirectional communication (one wire pair for receive and another one for transmit) only allows for round-trip measurements. In contrast, AEtas uses a bidirectional approach where the point-to-point delay on each individual transmission line can be determined separately in both directions. This allows to measure static delay asymmetries induces by transceivers as well as dynamic asymmetries caused for example by changing cable lengths. As the regular Ethernet communication must not be impaired, the AEtas signal is embedded using a modulation scheme highly orthogonal to 100Base-TX, namely using a chirp spread spectrum approach. This approach creates an additional logical communication channel that is solely used by the AEtas synchronization protocol, making it independent from the network load of the regular Ethernet communication.
An important outcome of the project was an FPGA based prototype board, developed in close cooperation with the project partner Oregano Systems. The algorithms and approaches developed throughout the project were evaluated using simulation and laboratory setups. Final laboratory measurements showed that AEtas is able to achieve synchronization accuracies in the range of 100 picoseconds.
An appealing feature of AEtas is that it can provide synchronization as a service where the host requests the accurate time-of-day without knowledge of the underlying communication structure. This allows for using the system with high synchronization accuracy down to the nanosecond range in low-end performance embedded microcontroller solutions. ** This project is co-funded by FFG within the FIT-IT programme.
|Duration||01/01/2011 - 30/06/2013|
|Principle investigator for the project (University for Continuing Education Krems)||Dipl.-Ing. Dr. Martin Brandl|
|Project members||Dipl.-Ing. Thomas Bigler DI Dr. Reinhard Exel|
Bigler, T.; Exel, R. (2013). Out-of-band asymmetry removal for high accuracy clock synchronization in 100Base-TX. Precision Clock Synchronization for Measurement Control and Communication (ISPCS), 2013 International IEEE Symposium on: 29--34
Ferrari, P.; Flammini, A.; Sisinni, E.; Depari, A.; Rizzi, M.; Exel, R.; Sauter, T. (2013). Timestamping and Ranging Performance for IEEE 802.15.4 CSS Systems. Instrumentation and Measurement, IEEE Transactions on: 1-9
Exel, R.; Ring, F. (2013). Improved clock synchronization accuracy through optimized servo parametrization. Precision Clock Synchronization for Measurement Control and Communication (ISPCS), 2013 International IEEE Symposium on: 65--70
Ferrari, P.; Flammini, A.; Sisinni, E.; Depari, A.; Rizzi, M.; Exel, R.; Sauter, T. (2013). New test bench for evaluation of IEEE 802.15.4 CSS timestamping capabilities. Instrumentation and Measurement Technology Conference (I2MTC), 2013 IEEE International: 259--264
Mahmood, A.; Exel, R. (2013). Servo Design for Improved Performance in Software Timestamping-assisted WLAN Synchronization using IEEE 1588. Emerging Technologies Factory Automation (ETFA), 2013 IEEE 18th Conference on: 1--8
Out-of-band asymmetry removal for high accuracy clock synchronization in 100Base-TX
2013 International IEEE Symposium on Precision Clock Synchronization for Measurement Control and Communication (ISPCS), 25/09/2013