The availability of highly accurate and precise clock synchronization is a major pre-requisite for reliable operation and performance. Applications such as client-localization, smart grids, telecommunications, industrial control, process automation, etc. demand robust, highly accurate and precise synchronization. In contrast to previous attempts to enhance the fault tolerance and robustness of clock synchronization systems, the FFG supported HiProSync project utilizes end-device based redundancy, which is fully transparent to the existing network infrastructure and thus perfectly suited for retrofitting existing networks.

Application requirements for clock synchronization cover a wide range (from a few milliseconds to below 1 ns) which need to be met for the successful operation. In addition to achieving high accuracy, however, there is a need to maintain this performance in the presence of various faults in the network, such as the failure of nodes or links, and maintain the desired precision for synchronization.

Current solutions for clock synchronization robustness in existing networks offer only limited fault mitigation or would involve major hardware changes in the system. The favored way has been to use existing synchronization protocols such as network time protocol (NTP) and the IEEE 1588-2008 precision time protocol (PTP), and propose changes to fix certain faults by either by software modifications or by replacing the network infrastructure. Hence, there is a shortage of a solution which offers high precision and robust synchronization at the same time under the necessity to impose minimal changes to existing networks used for clock synchronization. The HiProSync project aims to overcome this gap and proposes end-devices based redundancy, which is fully transparent to the existing network infrastructure.

The robustness in the slaves themselves is achieved by enhancing the synchronization engine in the end devices, and enabling them to synchronize to multiple reference clocks simultaneously. The various reference clocks are continuously monitored and evaluated for the quality of their time information. One goal in the project is to design algorithms for fault and failure detection from these reference clocks, and then to mitigate the impact of these faults on the slave clocks without any loss of synchronization. The latter is achieved by combining time from the reference clocks in an adaptive fashion, which separate the faulty reference clocks from the good ones and take their time to maintain synchronization.

The concepts and algorithms designed in the project will be analyzed via simulation and real-time testing. This will include developing concepts for network and clock modeling. For the former, network traffic models for various situations will be analyzed. The latter will involve modelling error sources present in in real-life quartz oscillators such as frequency offset, drift, and random phase noise. These models will make the basis for a network-wide simulation environment to verify the algorithms designed for robust and fault-tolerant clock synchronization. The results from simulation will be validated not only in lab-based test setups, but also by analyzing synchronization quality over a wide-area network. Hence, with HiProSync, an end-node centric approach for robustness will be provided for synchronization. This makes our solution especially appealing for large-scale networks where retrofitting must be done efficiently and the network infrastructure is not under the control of the end device operator.


The project HiProSync (High Precision and Robustness in network-based Clock Synchronization, FFG 848467) ist co-funded by the FFG within the Bridg 1 programme.


Duration 01/04/2015 - 31/03/2018
Funding FFG
Program bridge 1

Department for Integrated Sensor Systems

Center for Distributed Systems and Sensor Networks

Principle investigator for the project (University for Continuing Education Krems) Dipl.-Ing. Albert Treytl
Project members Dipl.-Ing. Thomas Bigler Anetta Nagy, MSc Dipl.-Ing. Felix Ring


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Mahmood, A.; Exel, R.; Sauter, T. (2017). Performance of IEEE 802.11’s Timing Advertisement Against SyncTSF for Wireless Clock Synchronization. IEEE Transactions on Industrial Informatics, 13(1): 370-379

Mahmood, A.; Exel, R.; Trsek, H.; Sauter, T. (2017). Clock Synchronization Over IEEE 802.11—A Survey of Methodologies and Protocols. IEEE Transactions on Industrial Informatics, 13(2): 907-922

Wollschlaeger, M.; Sauter, T.; Jasperneite, J. (2017). The Future of Industrial Communication: Automation Networks in the Era of the Internet of Things and Industry 4.0. IEEE Industrial Electronics Magazine, 11(1): 17-27

Mitaroff-Szécsényi, J.; Priller, P.; Sauter, T. (2017). Compensating Software Timestamping Interference from Periodic Non-Interruptable Tasks. IEEE, 22nd IEEE International Conference on Emerging Technologies And Factory Automation (ETFA): 1-4


Communication aspects in distributed sensor systems

Seminar on Energy Efficient Distributed Sensor Systems for the Internet of Things, National Chiao Tung University, Hsinchu, Taiwan, 10/05/2017



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